1. Field of the Invention
The present invention relates to a shift register and a liquid crystal display (LCD) device using the shift register, to prevent a bias stress applied to a transistor, thereby preventing the transistor from being deteriorated.
2. Discussion of the Related Art
A Cathode Ray Tube (CRT), one of flat display devices, has been widely used for monitors of a television, a measuring machine and an information terminal. However, the CRT has limitations regarding both its size and weight. Accordingly, display devices such as a liquid crystal display (LCD) device, a field emission display (FED), a plasma display panel (PDP), and a light emitting display (LED) have been actively studied, which can substitute for the CRT.
The LCD device includes an LCD panel for displaying a picture image, and a driving circuit for applying a driving signal to the LCD panel.
The LCD panel includes a plurality of gate and data lines, wherein each of the gate lines is perpendicular to each of the data lines, to define a plurality of pixel regions which are provided with liquid crystal cells. The respective liquid crystal cells include pixel electrodes and common electrodes. The pixel electrodes are connected with any one of the data lines through source and drain terminals of thin film transistors which function as switching devices. Also, the gate terminal of the thin film transistor is connected with any one of the gate lines.
The driving circuit is comprised of a gate driver for driving the gate lines, and a data driver for driving the data lines. The gate driver sequentially supplies scan pulses to the gate lines, whereby the liquid crystal cells of the LCD panel are driven in sequence. The data driver supplies video signals to the data lines whenever the scan pulse is provided to any one of the gate lines. Accordingly, the LCD device displays images by controlling light-transmittance with an electric field applied between the pixel electrode and the common electrode according to the video signal applied to each of the liquid crystal cells.
The gate driver of the driving circuit uses a shift register so as to generate the scan pulses for sequentially driving the gate lines. Also, the data driver uses a shift register so as to generate sampling signals for sequentially sampling the inputted video signals by each clock. If the gate and data drivers, having the shift registers, are formed of polysilicon, they are mounted on the LCD panel.
FIG. 1 is a schematic view of showing a shift register according to the related art.
As shown in FIG. 1, a shift register according to the related art is comprised of ‘n’ stages ST1 to STn, which are connected with gate start pulse input lines, for receiving three clock signals among four clock signals C1 to C4. The first to fourth clock signals C1 to C4 are phase-delayed by each clock, and then are supplied through the respective input lines in the order of C4, C1, C2 and C3. Also, a gate start pulse GSP is supplied in synchronization with the fourth clock signal C4 by each frame.
The first stage ST1 outputs a first output signal S01 using the gate start pulses and the three clock signals among the four clock signals C1 to C4. Then, the second to n-th stages ST2 to STn, respectively, output second to n-th output signals S02 to S0n using the output signal S01 to SO(n−1) outputted from the prior stage ST1 to ST(n−1) and the three clock signals among the four clock signals C1 to C4. That is, the first to n-th stages ST1 to STn sequentially output the first to n-th output signals S01 to S0n of which phases are shifted.
The first to n-th output signals S01 to S0n may be used with the scan pulses for sequentially driving the gate lines of the LCD panel, or may be used with the sampling signals for sequentially sampling the video signals of the data driver.
FIG. 2 is a circuit view showing the first stage ST1 of FIG. 1. Referring to FIG. 2, the first stage ST1 is comprised of a first controller 32, a second controller 34, and an output buffer 36. The first controller 32 controls a first node Q according to the fourth clock signal C4 and the gate start pulse GSP. The second controller 34 controls a second node QB according to the third clock signal C3 and the gate start pulse GSP. Also, the output buffer 36 selectively outputs any one of the first clock signal C1 and a first supplying voltage VSS according to the voltages of the first and second nodes Q and QB.
The first controller 32 includes a first transistor T1, a second transistor T2, and a third transistor T3. In detail, the first transistor T1 of a diode type is connected with the gate start pulse input line. The second transistor T2 is connected with the first transistor T1, the fourth clock signal input line, and the first node Q. The third transistor T3 is connected with the second transistor T2, the first supplying voltage VSS, and the second node QB.
The second controller 34 includes a fourth transistor T4, and a fifth transistor T5. At this time, the fourth transistor T4 is connected with the second supplying voltage VDD input line, the third clock signal C3 input line, and the second node QB. The fifth transistor T5 is connected with the second node QB, the gate start pulse GSP input line, and the first supplying voltage VSS input line.
The output buffer 36 includes a sixth transistor T6, and a seventh transistor T7. At this time, the sixth transistor T6 selectively supplies the first clock signal C1 to the output line according to the voltage of the first node Q. The seventh transistor T7 selectively supplies the first supplying voltage VSS to the output line according to the second node QB. The seventh transistor T7 operates with the third transistor T3 of the first controller 32 according to the voltage of the second node QB.
As shown in FIG. 1, the first, third and fourth clock signals C1, C3, and C4 are supplied to the first stage ST1. In FIG. 3, the gate start pulse GSP and the first to fourth clock signals C1 to C4 are supplied in a positive type which has a swing voltage of about 25V, at least above 10V. Supposing that a potential of 17V is in a high state, a potential of −8V is in a low state, the first supplying voltage VSS applied to the first stage ST1 is about −8V, and the second supplying voltage VDD is about 17V.
An operation of the fist stage ST1 will be explained with reference to the driving waveform. During a period of ‘t1’, the gate start pulse GSP and the fourth clock signal C4 are in the high state, whereby the first and second transistors T1 and T2 are turned-on, and the first node Q is in a first high state H1. Accordingly, the sixth transistor T6 having the gate terminal connected with the first node Q is turned-on slowly. Thus, the third and seventh transistors T3 and T7 having the gate terminals connected with the second node QB are turned-off. In the period of ‘t1’, the first clock signal C1 of low state is supplied to the output line of the first stage ST1 through the sixth transistor T6.
During a period of ‘t2’, the gate start pulse GSP and the fourth clock signal C4 are in the low state, whereby the first clock signal C1 is in the high state. Thus, the first and second transistors T1 and T2 are turned-off, so that the sixth transistor T6 is turned-on. The first node Q is a floating state as the first and second transistors T1 and T2 are turned-off. Thus, the first node Q is bootstrapping according to the high-state voltage of the first clock signal C1 by a parasitic capacitance Cgs, generated between the gate and source terminals of the sixth transistor T6. Accordingly, the first node Q is in a second high state H2 which is higher than the first high state H1, whereby the sixth transistor T6 is turned on. As a result, the first clock signal C1 of the high state is supplied to the output line of the first stage ST1. Accordingly, the first stage ST1 outputs the output signal S01 of the high state.
During a period of ‘t3’, the first clock signal C1 is in the low state, and the second clock signal C2 is in the high state, wherein the voltage of the first node Q of the floating state is switched to the first high state H1, and the sixth transistor T6 is maintained in the turning-on state. Accordingly, the first stage ST1 outputs the first clock signal C1 of the low state through the sixth transistor T6, in which the first clock signal is outputted as the output signal S01.
During a period of ‘t4’, the third clock signal C3 is in the high state, whereby the fourth transistor T4 is turned-on. Thus, the second supplying voltage VDD is supplied to the second node QB. Accordingly, the third and seventh transistors T3 and T7 are turned-on at the same time. That is, the first supplying voltage VSS is supplied to the first node Q through the third transistor T3. The sixth transistor T6 is turned-off using the first supplying voltage VSS supplied to the first node Q. As a result, the first stage ST1 outputs the first supplying voltage VSS through the seventh transistor T7.
During a period of ‘t5’, only the fourth clock signal C4 is in the high state, whereby the second transistor T2 is turned-on, and the first, fourth and fifth transistors T1, T4 and T5 are turned-off. Accordingly, the first and second nodes Q and QB are floating, whereby the first and second nodes Q and QB are maintained in the prior state. Thus, in the period of ‘t5’, the third and seventh transistors T3 and T7 are turned-on, whereby the output signal S01 of the first stage ST1 outputs the first supplying voltage VSS in the same manner as the period ‘t4’.
Meanwhile, the second to n-th stages receive the output signals outputted from the prior stages ST1 to ST(n−1) as the gate start pulse GSP, and also receives three clock signals among the first to fourth clock signals C1 to C4, and then outputs the output signals S02 to S0n. That is, the second to n-th stages are operated in the same method as the first stage ST1.
Among the transistors of the respective stages ST1 to STn, the third and seventh transistors T3 and T7 are operated according to the voltage of the second node QB. That is, when driving the third and seventh transistors T3 and T7, a bias stress is applied to the third and seventh transistors T3 and T7. That is, the bias stress is applied to the third and seventh transistors T3 and T7 except during the period of outputting the high-state signal in one frame.
The third and seventh transistors T3 and T7 are deteriorated due to the bias stress. Accordingly, as shown in FIG. 4A, if a positive bias stress is applied to the third and seventh transistors T3 and T7, the output-current characteristics are shifted to the right side according to the gate voltage. That is, as the output-current characteristics are shifted to the right side according to the gate voltage, the gate voltage must be increased in order to output the same-level current.
Meanwhile, as shown in FIG. 4B, if a negative bias stress is applied to the third and seventh transistors T3 and T7, the output-current characteristics are shifted to the left side according to the gate voltage. That is, as the output-current characteristics are shifted to the left side according to the gate voltage, the gate voltage must be increased in order to output the same-level current.
Also, the first to fourth clock signals C1 to C4 are sequentially applied to the respective stages ST1 to STn without regard to the frame. Thus, the third and seventh transistors T3 and T7 may deteriorate due to the bias stress by the clock signals C1 to C4.
To prevent the deterioration of a transistor, it is necessary to prevent the bias stress from being applied to the third and seventh transistors T3 and T7, which are connected with the second node QB of the respective stages ST1 to STn.